This paper presents a detailed two-dimensional numerical simulation study on the punchthrough characteristics of advanced self-aligned bipolar transistors utilizing a sidewall spacer technology. Particular emphasis is placed on the effect of the sidewall spacer thickness. Perimeter punchthrough due to insufficient extrinsic-intrinsic base overlap is shown to be a major concern. The tradeoff between the punchthrough current and the maximum surface electric field in the depletion region of the extrinsic base-emitter junction, which relates closely to the perimeter tunneling current, is discussed. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.