About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
Journal of High Speed Networks
Paper
On the design of a multigigabit ip router
Abstract
The emergence of gigabit speed networks hinges upon the existence of high performance internetworking units, such as JP routers. In this paper, we present an architecture and we discuss the implementation of a multigigabit JP router. For this implementation, two special purpose VLSI chips are required; the rest can be built using off-the-shelf components. JP header processing of received packets is handled by a specialized chip. Memory management, another well-known performance bottleneck, is simplified and efficiently implemented using special VLSI support. Searching for the next hop address in the routing table, which is the major contributor to the delay in traditional JP protocol implementations, is significantly reduced by using a special configuration of Content Addressable Memories (CAMs). © 1994 IOS Press and the authors.