About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
MWSCAS 2003
Conference paper
ON NETWORKING MULTITHREADED PROCESSOR DESIGN: HARDWARE THREAD PRIORITIZATION
Abstract
Ab8tract- Packet processing applications in networking equipment must fulfill very high throughput requirements. At the same time, packet processing differentiation by means of packet classification, such as voice vs. email, or DiffSeru, must be obeyed. An efficient way to fulfill both requirements is to use numerous hardware threads combined with thread prioritization. This paper proposes a new thread prioritization method for a hardware multithreaded processor. The originality of the method is identified in the derivation mechanism of the thread priorities, which is based on inputs from three distinct sources; namely, the threads themselves, a control unit such as an operating system, and external sources such as timers or synchronization coprocessors. These sources are explicitly selected to fulfill the requirements of their distinct nature, namely software, middleware and hardware. The proposed method achieves the desired thread differentiation without hindering performance or increasing costs, as demonstrated by initial experimental results.