Jae-Joon Kim, Keunwoo Kim, et al.
ESSDERC 2006
Numerical simulation-based study of double-gate (DG) field-effect transistors (FETs) leads to the possibly viable concept of extremely scaled but nonself-aligned DG CMOS. Predictions of off-state current, on-state current, and circuit performance, accounting for short-channel effects and energy-quantization effects, in 25-nm DG FETs suggest that moderate back-gate underlap does not severely undermine the superior performance and leakage current of nanoscale DG CMOS relative to those of bulk-Si CMOS. The reverse back-gate biasing scheme for leakage reduction in DG CMOS is shown to be much more efficient than the reverse body biasing scheme in bulk Si even with moderate back-gate underlap. © 2005 IEEE.
Jae-Joon Kim, Keunwoo Kim, et al.
ESSDERC 2006
Keunwoo Kim, R.V. Joshi, et al.
ISLPED 2003
Marwan H. Khater, Zhen Zhang, et al.
IEEE Electron Device Letters
Jin Cai, Tak Ning, et al.
IEEE International SOI Conference 2008