Sub-15 ps charge-buffered active-pull-down ECL/NTL circuits
Ken Chin, Ching-Te Chuang, et al.
CICC 1992
This brief paper presents a high-speed low-power non-threshold-logic (NTL) based push-pull logic circuit featuring a complementary emitter-follower driver. Compared with the standard NTL circuit, the circuit offers a much better balance between the pull-up and pull-down delay, improved scalability, and superior load driving capability. Simulation results based on a 0.8-μm double-poly self-aligned complementary bipolar technology indicate that at a power consumption of 1.22 mW/gate, the circuit offers 2.4× improvement in the pull-down delay of a loaded gate and 4.0× improvement in the load driving capability over the standard NTL circuit. The design and scaling considerations of the circuit are discussed. © 1991 IEEE
Ken Chin, Ching-Te Chuang, et al.
CICC 1992
Rajiv V. Joshi, Keunwoo Kim, et al.
VLSID 2007
Chunjian Ni, Rajiv V. Joshi, et al.
ASME Electronic and Photonics Packaging Division 2007
Rajiv Joshi, Rouwaida Kanj, et al.
ISLPED 2007