Keunwoo Kim, J.G. Fossum, et al.
SISPAD 2003
Leakage power and input pattern dependence of leakage for extremely scaled (Leff = 25 nm) double-gate (DG) circuits are analyzed, compared with those of conventional bulk-Si counterpart. Physics-based numerical two-dimensional simulation results for DG CMOS device/circuit power are presented, identifying that DG technology is an ideal candidate for low-power applications. Unique DG device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design tradeoffs for DG CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for DG device, considering state dependency, show that leakage currents for DG circuits are reduced by a factor of over 10x, compared with bulk-Si counterpart. © 2005 IEEE.
Keunwoo Kim, J.G. Fossum, et al.
SISPAD 2003
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ICSICT 2022
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