Novel circuits to improve SRAM performance in PD/SOI technology

Abstract

A novel circuit technique was presented to improve the read performance of static random access memory (SRAM) storage. The technique was used to suppress parasitic bipolar currents in partially depleted (PD) silicon on insulator (SOI) technology. The concepts were demonstrated by employing 1.5 V, 0.18 μm SOI technology. Simulation results indicated an increase in read current and performance by 18% at higher temperatures and by 24% at lower temperatures.