Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?

Abstract

Monte Carlo simulation is used to explore the characteristics of an n-channel MOSFET at the presently perceived limits of scaling. This dual-gated 30 nm gate-length FET is found to have excellent characteristics for use in digital logic, including a transconductance as high as 2300 mS/mm and an estimated ring-oscillator delay of 1.1 ps. The various motivations for this device design are discussed, illuminating the reasons for claiming that it is at the limits of scaling.