Device Research Conference 2018
Conference paper

Monolithic Integration of III -V on silicon for photonic and electronic applications

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As we increasingly move beyond conventional silicon CMOS towards more hybrid technology platforms there is a rising interest in integrating other materials on the Si substrate. Co-integrated III-V materials could strongly enhance electronic properties by providing increased electron mobility or tunable heterostructures or add additional functionality for silicon photonics via integrated direct bandgap materials [1], [2]. We have developed a method for monolithic III-V integration on Si, where we grow III-V material within lithographically defined oxide cavities [3]-[7]. This provides us with a high degree of control and versatility, while eliminating some of the constraints associated with either buffer layers or traditional selective area growth of nanowires. As shown in Fig. 1 this method has been employed to demonstrate various electronic devices ranging from high performance InGaAs nFET [7], ballistic transport in nanowires [8] to complementary III-V heterostructure Tunnel FETs (TFETs) where we have demonstrated a scalable platform for complementary TFETs [9], [10]. Recently we have also expanded this technology to optically active devices, enabling monolithically integrated micro-cavity GaAs [11], [12] and InGaAs lasers [13].