Minimizing via coupled noise in high performance thermal conduction module design

Abstract

In the design of thermal conduction modules, chips are interconnected through thin-film layers and glass-ceramic layers. The total amount of noise on the package consists of not only the crosstalk between adjacent signal lines in the X and Y directions, but also the coupled noise between adjacent pins and vias in the Z direction. While the crosstalk between adjacent wires can be minimized by reducing wire length and increasing wire spacing, the via noise problem has never been considered during layout design. This paper introduces the via noise constraints for physical design, and proposes a net ordering and layer assignment method to minimize the via coupled noise in thermal conduction module (TCM) design.