Manufacturability versus reliability issues relevant to interconnect metallizations

Abstract

Interconnections on silicon-based integrated circuits are almost exclusively aluminum alloys (Al-Si, Cu and various other solutes, e.g., Pd, Sc). The effects of film microstructure (grain size, grain size distribution, crystallographic texture and precipitate distribution) on the reliability of single level Al metallization has been well established. The final film microstructure obtained is dependent on both the deposition conditions and the thermal history during the manufacturing process. This paper will consider the role of microstructure in multi-level interconnects consisting of (1) Al(Cu) lines (in SiO2) with W and/or Al(Cu) studs and (2) an all Cu/polyimide multi-level structure. Methods for microstructure optimization during manufacturing of both Al and Cu based multi-level structures are explored. The variables important in determining the reliability of submicrometer single level versus multi-level structures and reliability testing methods (e.g., samples with versus without reservoirs and wafer level techniques) will be reviewed. Two relevant questions raised are; (1) What can be done during manufacturing to 'build-in' reliability?, and (2) What are the trade-offs between manufacturing complexity (i.e., cost) and inherent reliability?