G.L. Bona, P. Buchmann, et al.
IEEE Photonics Technology Letters
A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively. © IEE 2005.
G.L. Bona, P. Buchmann, et al.
IEEE Photonics Technology Letters
W. Hunziker, W. Vogt, et al.
IEEE Photonics Technology Letters
M. Kossel
Electronics Letters
A. Herkersdorf, P. Buchmann, et al.
International Zurich Seminar on Broadband Communications 2000