Interconnect-centric array architectures for minimum SRAM access time

Abstract

Generic and physical models for static random access memory (SRAM) time access were applied to explore the impact of various SRAM cache organization on its performance. These models were used to couple the hierarchical architectures with wire-lengths and fan-outs along critical paths to decode and sense data. The proposed model was also used to calculate the optimal array architectures that minimized the decode and sense delays by balancing decreasing interconnect delays.