IEDM 2018
Conference paper

InGaAs-on-Insulator FinFETs with Reduced Off-Current and Record Performance

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In this work, we demonstrate InGaAs-on-lnsulator FinFETs on silicon with optimized on/off trade-off showing record performance. This is achieved by using carefully designed source/drain spacers and doped extensions to mitigate the off-current, typically high in narrow band-gap materials, as part of a CMOS compatible replacement-metal-gate process flow. Using this technology, devices with L G= 20 nm, spacers width of 10 nm and W fin=15 nm achieve record high on-current of 350 μ Aμm( I OFF=100 n Aμm and V DD=0.5 V), for scaled III-V FETs on Si, enabled by an access resistance of 220 Ω.μ m, SS sat=78 mV/ decade and g m =1.5 mSμm. We analyze the impact of spacers thickness, W fin and LG on device performance. 2D TCAD simulations provide further insights into device functionality and about the dominant off-state leakage mechanisms.