Hybrid III-V/SiGe technology: Improved n-FET performance and CMOS inverter characteristics

Abstract

Recently, hybrid III-V/SiGe CMOS circuits have been demonstrated. Reported InGaAs n-FET performance was severely degraded by the CMOS flow compared to reference devices processed individually. We report on the recovered n-FET performance and its impact on CMOS inverters. In addition, we study the influence of back-bias on short-channel effects immunity and inverter transfer characteristics.