Publication
EDTM 2017
Conference paper

How non-ideality effects deteriorate the performance of tunnel FETs

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Abstract

Physics-based TCAD simulations of measured vertical and lateral InAs/Si hetero nanowire tunnel FETs are presented to demonstrate the effect of major non-idealities on slope and ON-current. The Dit limit for sub-thermal TFET operation is predicted, and it is shown that a high defect density at the InAs/Si interface can result in a slope close to 60 mV/dec due to thermionic emission in an arising MOSFET with the intrinsic Si region as gated channel.

Date

Publication

EDTM 2017

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