A. Kerber, E. Cartier, et al.
Journal of Applied Physics
Yttrium lanthanum silicate was formed in direct contact with silicon after a rapid thermal annealing at 1000°C in metal-oxide-semiconductor capacitors leading to an equivalent oxide thickness (EOT) of 7.7 Å. This represents one of the lowest EOT value reported for a gate-first process with non Hf-based dielectric. The silicate is formed by interdiffusion of La2 O 3 and YOx layers and interfacial SiO2 consumption. Yttrium incorporation reduces the leakage current density as well as the large negative flatband voltage (Vfb) shift that is associated with lanthanide-based dielectrics. The Vfb value can be appropriately tuned for n-type field-effect transistor operation by changing the silicate composition. © 2011 American Institute of Physics.
A. Kerber, E. Cartier, et al.
Journal of Applied Physics
M. Copel, E. Cartier, et al.
Applied Physics Letters
V. Narayanan, A.C. Callegari, et al.
VLSI Technology 2004
Eduard Cartier, Amlan Majumdar, et al.
ESSDERC 2017