High performance SOI/Cu SRAMs and memories in microprocessors

Abstract

This paper describes applications of Silicon on Insulator (SOI) technology to high performance on-chip memories (e.g. SRAMs and register files etc.). The primary focuses are on the important and unique issues in SOI technology such as performance gain, history effect, power reduction, pulsewidth control and self-heating. The effects on the interconnect performance and reliability are also discussed. The hardware data show that Partially Depleted (PD) SOI technology results in 20-25% and 18-22% improvement in the performance over bulk cmos using 0.25μm and 0.18μm technology nodes respectively. Power reduction of 7% to 8% over bulk technology is realized. Self-heating in SOI can cause device and interconnect temperatures to rise more than 10° -12° C.