High performance CMOS circuit techniques for the G-4 S/390 microprocessor

Abstract

This paper describes the CMOS circuit techniques used in the design of the high performance Generation-4 S/390 microprocessor. Successful system operation at frequencies up to 400 MHz was achieved through careful static circuit design and timing optimization, along with the limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. A variety of innovative full-custom circuit techniques were used in the dataflow design. Timing-driven synthesis of the control logic provided maximum flexibility with minimum turn-around time, while still matching the performance level set by the custom parts of the design. The on-chip L1 cache was designed extensively with self-resetting CMOS (SRCMOS) circuitry to provide a 2.0 ns access time and up to 500 MHz operation.