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Publication
IEEE Topical Meeting EPEPS 1997
Conference paper
Hierarchical power supply distribution model for full-chip switching noise analysis
Abstract
This paper describes the use of a 12×12 SCM power supply distribution model, a 50×50 on-chip power bus model, and a distributed switching circuit model to analyze the on-chip power supply noise for high-performance VLSI design. The integrated model provides a complete analysis of the Vdd distribution, and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.