IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Generation of Performance Constraints for Layout

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In this paper we present methods for generating bounds on interconnection delays in a combinational network having specified timing requirements at its input and output terminals. An automatic placement program which uses wirability as its primary objective could use these delay bounds to generate length or capacitance bounds for interconnection nets as secondary objectives. Thus, unlike previous timing-driven placement algorithms described in the literature, the desired performance of the circuit is guaranteed when a wirable placement meeting these objectives is found. We also provide fast algorithms which maximize the delay range, and hence the margin for error in layout, for various types of timing constraints. © 1989 IEEE