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Publication
Microprocessors and Microsystems
Conference paper
Flow control scheduling
Abstract
We address a problem associated with credit flow control (FC) schemes for buffered switches, namely, the issue of FC bandwidth and FC optimization, i.e. how many and which credits to return per packet cycle. Using simulations, we show that, under the assumption of bursty traffic with uniform or nonuniform destinations, the number of credits to be returned can be reduced to one, independent of switch size and without loss in performance. Moreover, we introduce the concepts of credit contention and credit scheduling. We analyze five credit-scheduling strategies for a range of system and traffic parameters. Our results demonstrate that with a proper credit scheduler the average packet delay is much lower than with conventional schemes. © 2003 Elsevier Science B.V. All rights reserved.