FEOL technology trend

Abstract

Trends in front-end-of-line technology are discussed. At the chip level, many of the important parameters are published in the National Technology Roadmap for Semiconductors in 1994. At the device and circuit level, both bipolar and CMOS are scalable. However, the large standby power of bipolar circuits severely limits the integration level of bipolar chips. The inherently low standby power of CMOS, on the contrary, allows the integration level of CMOS circuits to continue increasing with scaling. In reality, both the electric field and power density of CMOS devices have been gradually rising over the generations owing to non-scaling effects of thermal voltage and silicon bandgap. As power supply voltage reaches 1.5 V and below, circuit performance can only be gained at the expense of higher active or standby power of the chip. Implications of device scaling on contact and silicide technology are addressed. Trends of local and global interconnect scaling are discussed. © 1998 Elsevier Science S.A.