Fault simulation of logic designs on parallel processors with distributed memory

Abstract

The authors describe a novel parallelization technique for fault simulation that is suited for message-passing-based parallel processors. The problem is parallelized by first casting it in data-flow form and then constructing a data-flow emulator for message-passing systems. By letting the number of nodes in the parallel processor grow linearly with C, the size of the design, the fault simulation time on a mesh-connected processor grows only as Cr+δ-0.5, rather than as C1+δ, as on a uniprocessor; r is Rent's exponent and is less than 1.0 and typically on the order of 0.7, and δ is a small positive constant on the order of 0.5 or less. The algorithm has been implemented and exercised on the IBM VICTOR multiprocessor. The performance has been measured for several logic designs as a function of the number of nodes in the parallel processor.