Publication
IEEE Design and Test
Paper

Fair and comprehensive benchmarking of machine learning processing chips

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Abstract

With the rise of custom silicon chips for AI acceleration, fair and comprehensive benchmarking of hardware innovations has become increasingly important. While benchmarking at the application- and system-level provides the most complete picture of trade-offs across multiple design dimensions, this can hide the impact of innovations at lower levels. Moreover, system-level benchmarking is not always feasible, especially for academic and industrial research chips. Benchmarking machine learning chips at lower abstraction levels is therefore still useful and common practice, making use of architecture- or circuit-level metrics. Yet the selection of good metrics and benchmarking conditions is critical, as these strongly influence the correlation between the observed performance benefits and the final system-level benefits. This paper provides an overview of benchmarking strategies at different abstraction levels, and discusses best practices and pitfalls to-be-avoided. We then propose to combine this diligent benchmarking at the appropriate individual abstraction level, with careful extrapolation to the system-level to also gauge impact at that topmost level. While the paper focuses on neural network inference workloads, many guidelines discussed here are applicable to the broader class of machine learning chips.

Date

01 Jan 2021

Publication

IEEE Design and Test

Authors

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