Full metal gate with borderless contact for 14 nm and beyond
Soon-Cheon Seo, L.F. Edge, et al.
VLSI Technology 2011
Cu films were directly deposited on Ru to check the feasibility of this process for Cu back-end-of-the-line integration beyond 32-nm technology nodes. Feature-fill enhancement was observed from the direct electroplating process as compared to the conventional one with the Cu electroplating performed on a PVD Cu seeding layer. Reasonable parametric yields were demonstrated for the direct electroplating process. The electromigration (EM) resistance of the directly plated Cu lines was degraded relative to that observed on the conventionally plated Cu lines. The observed EM resistance degradation is attributed to a weak interface between Ru/Cu, which can be caused by impurities from the electroplating process. © 2010 IEEE.
Soon-Cheon Seo, L.F. Edge, et al.
VLSI Technology 2011
Steven Consiglio, H. Higuchi, et al.
IMCS 2021
C.-C. Yang, D. Edelstein, et al.
IITC 2009
Soon-Cheon Seo, Chih-Chao Yang, et al.
ADMETA 2008