Conference paper
Cross-layer system resilience at affordable power
Meeta S. Gupta, Jude A. Rivers, et al.
IRPS 2014
This paper provides: 1) a very brief motivation and technological trend data to show why hard and soft errors are expected to be of increasing concern in the future; 2) a summary review of chip-level error tolerance practices today-with a brief reference to IBM's POWER6 and POWER7 designs; 3) open research challenges and current solution approaches of promise, based on published literature; and 4) concluding remarks. © 2011 IEEE.
Meeta S. Gupta, Jude A. Rivers, et al.
IRPS 2014
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DATE 2012
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Meeta S. Gupta, Jude A. Rivers, et al.
IRPS 2014