Electrostatic analysis of carbon nanotube arrays

Abstract

In order to improve the performance of carbon nanotube field effect transistors (CNFETs), a nanotube array should be used. For a densely packed array of nanotubes, screening by nearby tubes affects the capacitance per tube. The gate-to-channel capacitance for a nanotube array of three different gate electrode configurations was examined in this study. Simulation results show that a wrap-around gate gives the largest gate-to-channel capacitance among the three gate configurations. A bottom gate structure, in which carbon nanotubes are unpassivated, presents a distinct electrostatic disadvantage of the weakest gate control. For a top gate structure, we found that an optimum design point exists for the pitch, which is defined as the distance between the centers of adjacent nanotubes, to get the largest gate capacitance per unit area.