We have stressed AlGaN/GaN HEMTs (High Electron Mobility Transistors) under high-power and high-temperature DC conditions that resulted in various levels of device degradation. Following electrical stress, we conducted a well-established three-step wet etching process to remove passivation, gate and ohmic contacts so that the device surface can be examined by SEM and AFM. We have found prominent pits and trenches that have formed under the gate edge on the drain side of the device. The width and depth of the pits under the gate edge correlate with the degree of drain current degradation. In addition, we also found visible erosion under the full extent of the gate. The depth of the eroded region averaged along the gate width under the gate correlated with channel resistance degradation. Both electrical and structural analysis results indicate that device degradation under high-power DC conditions is of a similar nature as in better understood high-voltage OFF-state conditions. The recognition of a unified degradation mechanism provides impetus to the development of a degradation model with lifetime predictive capabilities for a broad range of operating conditions spanning from OFF-state to ON-state.