Efficient simulation of bipolar digital ICs

Abstract

High-performance logic circuitry for mainframe computers is most commonly implemented in the bipolar emitter-coupled logic (ECL) family. BiCMOS circuits are becoming increasingly common in digital applications. The simulation of such circuits with a general-purpose circuit analysis tool is very compute-intensive. An efficient simulation methodology for ECL bipolar designs is presented. By using an event-driven scheme to exploit the underlying latency in the circuit and by using simplified device models, efficient simulation is accomplished while staying within tolerable error bounds.