About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IEEE TCADIS
Paper
Efficient methodologies for 3-D TCAD modeling of emerging devices and circuits
Abstract
Over the past decade, 3-D process simulation, which is central to the 3-D Technology Computer-Aided Design (3-D TCAD) approach, has severely limited the scope and applicability of TCAD to circuits with a small number of field-effect transistors, owing to its prohibitively high computational costs for large layouts. Due to rapidly changing process recipes and shorter production cycles in the industry, design-time optimization and iterative layout-3-D TCAD exploration for yield-critical or yield-characterizing circuits, such as static random-access memories (SRAMs), ring oscillators, and others, is currently impossible in a practical time frame. In this paper, we architect a novel layout/process/device-independent TCAD methodology in the Sentaurus tool suite to overcome the process simulation barrier for accurate 3-D TCAD structure generation. We adopt an automated structure synthesis (SS) approach, thereby bypassing the need for repetitive 3-D process simulations for different layouts or different versions of the same layout. Results for 32-nm bulk process simulations versus SS and 32-nm silicon-on-insulator (SOI) hardware measurements versus corresponding synthesized structures indicate that the method is an excellent substitute to 3-D process simulation of large layouts, with extremely favorable time and memory scaling behavior. Finally, the robustness and scalability of the proposed abstractions are highlighted through the synthesis of 22-nm SOI 6T FinFET SRAMs and ring oscillator structures. © 1982-2012 IEEE.