Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis

Abstract

Automated design space exploration has become a promising approach for improving VLSI design quality and achieving a balance across a range of design closure objectives. However, it comes with the challenge of high compute resource cost in terms of CPU runtime, disk space, and memory requirements. This paper proposes an automated early scenario pruning (ESP) scheme that predicts the quality of results for synthesis scenarios at the early stages of the synthesis runs. Scenarios deemed non-competitive in terms of objective cost functions can be pruned prior to completion under the proposed framework. This flow reduces the compute resource cost significantly, especially for big and complex design blocks, making design exploration more efficient. The proposed framework is a layer on top of the logic and physical synthesis programs for a high-performance microprocessor design environment. Our experimental data on 14nm processor design blocks suggest over 80% pruning efficiency is possible while claiming approximately 20% savings in CPU time.