Demonstration of a high performance 40-nm-gate carbon nanotube field-effect transistor

Abstract

Carbon nanotubes (CNTs) are promising candidates for post-Si nano-electronics [1]. They are particularly attractive for high-speed applications due to their ballistic properties and high Fermi velocity (∼10 6 m/s) [2]. The small-signal switching speed of a transistor is determined by the intrinsic delay time τ =2πC G/g m, where C G is the gate capacitance and g m=dI d/dV gs is the transconductance. For carbon nanotube field-effect transistors (CNFETs), the highest g m reported so far is ∼ 27 μS by Javey et al. [3] using a dielectric film of 8-nm HfO 2 (κ=15). In their CNFET, the gate capacitance per unit length is estimated to be C G/L=1.8×10 -16 F/μm, resulting in a gate delay per unit length of τ/L=42 ps/μm. Here we present a high-performance CNFET with a delay time per unit length of τ/L=22 ps/μm, the smallest value reported for CNFETs to date. In order to further minimize the parasitic capacitances and lower the intrinsic gate capacitance, we utilize a dual-gate design and fabricate a 40-nm gate CNFET possessing excellent subthreshold and output characteristics, which is the shortest gate length for a well-tempered CNFET demonstrated so far. Figs. 1 and 2 show the subthreshold and output characteristics of a back-gated CNFET device measured at room temperature, respectively. The nanotubes used here are produced by arc discharge [4] and possess an average diameter of D∼1.8 nm. The schematic device structure is depicted in the inset of Fig. 1, where two Pd metal contacts form the source and drain electrodes and the p-doped Si substrate covered with a 10-nm SiO 2 layer is used as the gate. The CNFET possesses a subthreshold swing 5=140 mV/dec with an I ON/I OFF ratio > 10 5, and exhibits output characteristics similar to those of a regular p-MOSFET. Fig. 3 shows the CNFET transfer characteristics for a bias voltage V ds = -1.5 V measured at two temperatures, 90 K and 300 K. We note that measured currents I d are nearly identical for the two temperatures, even up to 350 K (data not shown here), indicating a carrier mobility almost independent of temperature and device reliability over a wide temperature range. In addition, the results in Fig. 3 illustrate excellent reproducibility of the CNFET characteristics without any shift of threshold voltage over time, which is essential for digital applications. When performing the measurements, we also simultaneously recorded the transconductance g m of the CNFET as a function of gate voltage V gs, as plotted in the inset of Fig. 3, exhibiting a peak value of g m∼12. 5 μS at V gs ∼ -0.5 V. Using the coplanar geometry, the gate capacitance of the CNFET is estimated by C G= 2πεε 0L/ln(2+4d/D), where d and ε are the thickness and the effective dielectric constant of the oxide, respectively. With the 10-nm SiO 2 gate oxide, the capacitance per unit length of our CNFET is given by C G/L ∼ 0.43×10 -16 F/μm, yielding a gate delay per unit length of τ/L=22 ps/μm, the smallest delay per unit length for CNFETs reported to date. We note that when decreasing the gate length in order to lower the intrinsic gate capacitance, it is also important to keep the parasitic capacitance small and avoid any short-channel effects. For the back-gated CNFET as shown in the inset of Fig. 1, the parasitic capacitance between gate, source and drain electrodes would, however, increase with decreasing source-drain distance. Here we demonstrate a dual-gate CNFET without short-channel effects for a gate length as short as 40 nm and a source/drain separation of 300 nm. The device image and the schematic structure are shown in Fig. 4. Dual-gate CNFETs have been fabricated and studied previously [5], and they possess several advantages over fully gated CNFETs, such as controllable polarities, a superior subthreshold swing, and improved off states. We note that the gate length can be varied independently in a dual-gate CNFET, regardless of the source/drain electrode separation. Therefore, these CNFETs afford aggressive gate length scaling to simultaneously reduce both the gate capacitances and the parasitic capacitance between gate and source/drain electrodes. Fig. 5 shows the drain current I d vs. Al gate voltage V gs-Al of a 40-nm dual-gate CNFET when the Si back gate voltage is kept at V gs-Si=-2.5 V to enable hole injection at the contacts, exhibiting a subthreshold swing S=80 mV/dec with an I ON/I OFF ratio > 10 5. Fig. 6 shows the device output characteristics for V gs-Si=-3.5 V, illustrating excellent device performance without short-channel effects. This is, to our knowledge, the shortest gate length that has been reported for a well-tempered (one that does not show short-channel effects) CNFET so far. In conclusion, we have fabricated a high-performance CNFET with the smallest gate delay of 22 ps/μm reported thus far. Using a dual-gate design, we demonstrated a 40-nm gate CNFET showing excellent subthreshold and output characteristics. © 2005 IEEE.