Decoder Architecture for Array-Code-Based LDPC Codes

We describe a decoder architecture intended for decoding array-code-based low-density parity-check (LDPC) codes using the sum-product algorithm (SPA). The advantages of the proposed architecture as compared to the fully parallel implementation of the SPA are: reduced memory size, avoidance of complex signal interconnect patterns, and ease of program-ability to accommodate various code parameters. These advantages are derived from exploiting the well-defined structure of the parity-check matrix of array-code based LDPC codes. Sum-product decoding with modified message-passing schedules are proposed to simplify the decoder implementation further.