Ernest Y. Wu, Baozhen Li, et al.
VLSI Technology 2014
Cu grain size analysis, electrical measurements, and electromigration reliability tests were carried out in 50 nm wide features to evaluate low temperature reflow anneals of physical vapor deposited Cu as an alternative metallization scheme for BEOL Cu/low-k integration. Comparable final Cu grain size is observed between control electroplated samples and reflow annealed samples, and observed line resistance reduction from the reflow annealed samples is attributed to higher purity within the Cu interconnects. Both electrical measurements and electromigration test results confirm feasibility of this reflow anneal approach for BEOL Cu integration. © 2013 The Electrochemical Society.
Ernest Y. Wu, Baozhen Li, et al.
VLSI Technology 2014
James Kelly, X. Lin, et al.
JES
G. Tsutsui, Ruqiang Bao, et al.
IEDM 2016
C.-C. Yang, P. Flaitz, et al.
IEEE Electron Device Letters