Publication
DRC 2011
Conference paper

Compact model and performance estimation for tunneling nanowire FET

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Abstract

A compact model is presented which realistically reproduces TFET characteristics and allows complex circuit simulation and parameter optimization studies. The model has been applied to circuit simulations which reveal anomalous switching behavior, and to a multi-parameter optimization study which quantifies the power-performance advantage of the TFET over conventional MOSFETs. © 2011 IEEE.

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Publication

DRC 2011

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