Combined ramp voltage stress and constant voltage stress for optimal BTI voltage acceleration and lifetime modeling

Abstract

Bias temperature instability (BTI) is the primary reliability mechanism limiting further thinning of the dielectric with future CMOS scaling [1]. This has led to an increased emphasis on quick screening of different processes using Ramp Voltage Stress (RVS) [2], while Constant Voltage Stress (CVS) is typically utilized for more in depth modeling and lifetime projection. This strategy, though, severely underutilizes RVS and does not optimally combine the strengths of each test. Because the voltage is ramped during an RVS stress, a derivative of the RVS trace vs. ramp voltage yields an extremely detailed understanding of the voltage dependence of BTI. On the other hand, CVS directly measures the time evolution of BTI. This paper highlights the pitfalls of relying on just CVS for BTI lifetime projections and also demonstrates the complimentary nature of RVS and CVS for lifetime extraction. In addition, this paper will detail the tremendous benefit of a slow ramp RVS test, with ramp rates as low as 100 μV/s, for BTI modeling and lifetime extrapolation down to use conditions. © 2014 IEEE.