Due to their superior material properties over bulk silicon, low-dimensional materials have been actively explored as potential candidates to replace or complement silicon technology in post-Moore era. As the first low-dimensional based transistor technology widely studied, carbon nanotube field effect transistor (CNFET) technology is among the most promising candidates to outperform silicon in the advanced technology nodes, because of its potential to achieve higher speed, better gate control, and better energy efficiency. However, existing fabrication processes for most emerging low-dimensional material based technologies including CNFETs, suffer from imperfections, which lowers the device and circuit yield. This paper presents a quantitative methodology for estimating circuit-level yield of CNFET CMOS circuits, which takes into account imperfections of CNT substrates based on a recently developed CMOS-compatible self-assembly process. The impact of different types of process imperfection on circuit-level yield is analyzed. The paper also provides a methodology using device sizing optimization to effectively improve circuit level yields with minimal impact on area and energy delay product, consequently relaxing the process requirements to satisfy certain circuit-level yield target. It is shown that an 80% pass rate can be achieved even with today's process for various 4-stage cascade CMOS circuits through the proposed sizing optimization approach.