CMOS TECHNOLOGY SCALING, O.lpm AND BEYOND

Abstract

A projection of CMOS technology scaling and the expected performance, density, and power improvements are presented. Technology for scaling to sub-0.lpm effective channel length (Le#) is discussed, and the key barriers are examined. It is shown that device speed enhancement of about 3X, circuit density improvement of 8X, and 20-40X improvement in power-delay product (mWMPS) will be achieved by scaling the CMOS technologies down to the sub-0.lpm regime, operating in the 1V range, as compared with today's high performance 0.35pm devices at 3.3V. Such anticipated significant improvements in the silicon chip performance will continue to fuel the growth of the semiconductor industry for the next decade.