Conference paper
Learning Reduced Order Dynamics via Geometric Representations
Imran Nasim, Melanie Weber
SCML 2024
We report high-speed planar silicon p-i-n photodiodes fabricated on Silicon-on-Insulator (SOI) substrates. The devices were fabricated in standard CMOS technology with no additional fabrication steps required. The 250-nm finger-spacing devices exhibited 15- and 8-GHz bandwidths for devices processed on 200- and 2000-nm SOI substrates, respectively, at a reverse bias of -9 V. Quantum efficiencies of 12% and 2% were measured on the 2- and 0.2-μm thick SOI, respectively. The dark current was 5 pA for -3 V bias and 500 μA for -9 V bias.
Imran Nasim, Melanie Weber
SCML 2024
Ellen J. Yoffa, David Adler
Physical Review B
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Surface Science
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Micro and Nano Engineering