Circuit and technique for characterizing switching delay history effects in silicon-on-insulator logic gates

Abstract

A circuit and measurement technique with one can measure history effects dominated by either the output rising (pMOS) or output falling (nMOS) characteristics of a multiple-input silicon-on-insulator gate was discussed. Multiplexing was used to enable placement of a number independently addressable DUTs with complexity up to four inputs, within a single macro. The steady state pullup and pulldown delays for static CMOS logic gates on a chip fabricated in 0.18 μm were studied. Analysis shows that for the pulldown both the 1 SW and 2 SW delays decreased somewhat with increasing period.