With the increasing demand for higher bandwidth, network operators are updating their devices to support 40GE/100GE standards. Besides, next generation 400GE and 1TE standards are also in discussion, which pose big challenges to network chip design. Packet processing, packet buffering, switch fabric and chip interfaces are main challenges in network chip design. Among them, packet buffer might be the top problem because of the well known 'Memory Wall'. IBM solves the problem by providing a highly efficient chip interface, innovative memory technologies and advanced design process. In this paper, we address the bottleneck of the traffic manager chips which perform high performance packet buffering. Based on the analysis, we show how to solve the chip implementation difficulties to meet next generation bandwidth requirements. © 2013 IEEE.