CHARACTERIZATION AND MODELING OF A LATCHUP-FREE 1- mu M CMOS TECHNOLOGY.

Abstract

A 1- mu m CMOS technology using thin p/p** plus epi and shallow retrograde n-well is demonstrated to be latchup free since the holding voltage for latchup is higher than the 5-V power supply. Good agreement is obtained between the experimental result and simulations using a two-dimensional finite-element numerical analysis program. The sensitivity of latchup holding voltage to epi thickness and other structural parameters is also studied in the simulation.