Challenges of gate stack TDDB in gate-allaround nanosheet towards further scaling

Abstract

In this work, we present a comprehensive study on the gate stack TDDB challenges in Gate-all-around (GAA) nanosheet (NS) transistors (FETs), including volume-less Multiple Vt (Multi-Vt) integration and patterning, the performance and reliability trade-off in inner spacer (IS) module, and the impact from Si channel geometry on gate stack reliability, which is important elements in GAA NS. These scaling associated challenges served as strong motivators and will continue to drive process-reliability co-optimization efforts towards optimum performance while preserving robust TDDB reliability.