Abstract
In multilevel storage (MLS) the analog properties of CCDs are used to store more than one bit of information in a charge packet. For N bits in a packet, bit density increases by N at the cell level, but somewhat more slowly at the chip level due to the increased complexity of the launch and sense circuitry. However, the sense signal decreases rapidly with increasing N; the number of distinguishable charge levels required goes as 2 N and the nominal separation between adjacent levels goes as 1/(2-1), decreasing by more than a factor of two for each additional bit. The worst case sense signal is further reduced by tolerances on the information and reference levels resulting from circuit and device tolerances, leakage current and charge transfer inefficiency.