In Ccd multilevel storage, more than one bit of information is stored in a charge packet. Requirements for CCD MLS systems are described, and circuits for the encoding and decoding of charge packets which operate essentially independent of device parameter and geometric tolerances are presented. 3-bit operation on a short shift register loop is demonstrated. Requirements on leakage and transfer in-efficiency for 2- and 3-bit MLS are discussed. Copyright © 1981 by The Institute of Electrical and Electronics Engineers, Inc.