CAD for double patterning lithography

Abstract

Nanopatterning with 193nm lithography equipment is one of the most fundamental challenges for future scaling beyond 22nm while the next-generation lithography, such as EUV (Extreme Ultra-Violet) lithography still faces tremendous challenges for mass production in the near future. As a practical solution, double patterning lithography (DPL) has become a leading candidate for 16nm lithography process. DPL poses new challenges for overlay control, layout decomposition, and physical design compliance and optimization. In this paper, we will discuss challenges and some recent results in DPL aware timing analysis, layout decomposition, and layout optimization.