Assessment of true worst case circuit performance under interconnect parameter variations

Abstract

The complicated manufacturing processes dictate that process variations are unavoidable in today's VLSI products. Unlike device variations, which can be captured by worst/best case corner points, the effects of interconnect variations are context-dependent, which makes it difficult to capture the true worst-case timing performance. This paper discusses an efficient method to explore the extreme values of performance metrics and the specific parameters that will create these extreme performances. The described approach is based on a iterative search technique which facilitates its proper search direction by calculating an explicit analytical approximation model.