Conference paper
FPGA-based coprocessor for text string extraction
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
A method for multilevel validation and testing of architectural timing models (timers) coded to predict cycles-per-instruction performance of CMOS RISC processors, is described. Establishment of cause and effect relationships in terms of modal defects and associated fault signatures, verification of steady-state behavior pipeline flow against analytically predicted signatures using a derived application-based test loop kernels and verification of the 'core' parameters of pipeline-level machine organization using derived synthetic test cases, are emphasized.
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
Gal Badishi, Idit Keidar, et al.
IEEE TDSC
B. Wagle
EJOR
György E. Révész
Theoretical Computer Science