Charles H. Bennett, Aram W. Harrow, et al.
IEEE Trans. Inf. Theory
A method for multilevel validation and testing of architectural timing models (timers) coded to predict cycles-per-instruction performance of CMOS RISC processors, is described. Establishment of cause and effect relationships in terms of modal defects and associated fault signatures, verification of steady-state behavior pipeline flow against analytically predicted signatures using a derived application-based test loop kernels and verification of the 'core' parameters of pipeline-level machine organization using derived synthetic test cases, are emphasized.
Charles H. Bennett, Aram W. Harrow, et al.
IEEE Trans. Inf. Theory
Donald Samuels, Ian Stobert
SPIE Photomask Technology + EUV Lithography 2007
Alessandro Morari, Roberto Gioiosa, et al.
IPDPS 2011
Apostol Natsev, Alexander Haubold, et al.
MMSP 2007