Performance test case generation for microprocessors
Pradip Bose
VTS 1998
A method for multilevel validation and testing of architectural timing models (timers) coded to predict cycles-per-instruction performance of CMOS RISC processors, is described. Establishment of cause and effect relationships in terms of modal defects and associated fault signatures, verification of steady-state behavior pipeline flow against analytically predicted signatures using a derived application-based test loop kernels and verification of the 'core' parameters of pipeline-level machine organization using derived synthetic test cases, are emphasized.
Pradip Bose
VTS 1998
S.M. Sadjadi, S. Chen, et al.
TAPIA 2009
Rajiv Ramaswami, Kumar N. Sivarajan
IEEE/ACM Transactions on Networking
Kaoutar El Maghraoui, Gokul Kandiraju, et al.
WOSP/SIPEW 2010