Architectural improvements for a data-driven VLSI processing array

In this work we explore three modifications to the architecture of a Data-Driven VLSI array of processors, previously introduced in Koren et al. (IEEE Computer21, 10 (Oct. 1988), 30-43). These modifications are geared toward improving the array utilization, as well as the performance of the mapped algorithms. The first modification considered increases the internal parallelism present in each array processing element, allowing it to simultaneously execute two instructions. A second modification improves the connectivity between processing elements by adding wires and switches between these elements. The third modification creates blocks of processing elements, featuring tighter coupling and faster communication, to take advantage of algorithm locality. Each change is evaluated by asserting its impact on the mapping of algorithms onto the modified array. © 1993 Academic Press, Inc.